G Abarajithan

PhD candidate (CE) building parameterized RTL subsystems (AXI SoCs, DMA control, accelerators) and end-toend SoC integration (FPGA+ASIC flows). Current work develops Hyperflow-guided hardware security fuzzing with information-flow tracking to expose vulnerabilities in Out-of-Order CPUs and SoC fabrics.

Poster Series: Chemistry Reactions (High School)

less than 1 minute read

I created these charts to prepare for my GCE A/L Examinations. When I graduated from school, I redesigned them in Powerpoint and printed them into charts.