PhD candidate (CE) building parameterized RTL subsystems (AXI SoCs, DMA control, accelerators) and end-toend SoC integration (FPGA+ASIC flows). Current work develops Hyperflow-guided hardware security fuzzing with information-flow tracking to expose vulnerabilities in Out-of-Order CPUs and SoC fabrics.
![My Paper-Writing Workflow [Inkscape, Python, Mendeley, VSCode, Git]](https://pub-0718e0124bee4fb880ecad10710509d5.r2.dev/content/images/2021/11/53-3.png)
