• Skip to primary navigation
  • Skip to content
  • Skip to footer
Abarajithan G
  • Publications
  • Engineering
  • Teaching
  • Travel
  • Other
  • Tags
  • Posts
    G Abarajithan

    G Abarajithan

    PhD candidate (CE) building parameterized RTL subsystems (AXI SoCs, DMA control, accelerators) and end-toend SoC integration (FPGA+ASIC flows). Current work develops Hyperflow-guided hardware security fuzzing with information-flow tracking to expose vulnerabilities in Out-of-Order CPUs and SoC fabrics.

    • Website
    • GitHub

    Technical Projects

    CocoTB: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub

    CocoTB: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub

    April 4, 2022
    Neural Chip Design [4/4: SoC Integration & Firmware]

    Neural Chip Design [4/4: SoC Integration & Firmware]

    January 29, 2022
    Neural Chip Design [3/4: RTL Design & Verification]

    Neural Chip Design [3/4: RTL Design & Verification]

    January 29, 2022
    Neural Chip Design [2/4: Golden Model]

    Neural Chip Design [2/4: Golden Model]

    January 29, 2022
    Neural Chip Design [1/4: Overview]

    Neural Chip Design [1/4: Overview]

    January 28, 2022
    Vision-Based Adaptive Traffic Control on an MPSoC [ARM+FPGA]

    Vision-Based Adaptive Traffic Control on an MPSoC [ARM+FPGA]

    January 28, 2022
    My Paper-Writing Workflow [Inkscape, Python, Mendeley, VSCode, Git]

    My Paper-Writing Workflow [Inkscape, Python, Mendeley, VSCode, Git]

    November 21, 2021
    Startup: Web-Based Traffic Analytics

    Startup: Web-Based Traffic Analytics

    August 19, 2020
    SOC Design to Apply Two 7x7 Kernels to a 1080p YUV Video Feed at 30 FPS

    SOC Design to Apply Two 7x7 Kernels to a 1080p YUV Video Feed at 30 FPS

    October 19, 2019
    Serial System Bus + Protocol

    Serial System Bus + Protocol

    May 18, 2019
    Solving Schrödinger's Equation in 1,2,3-D with MATLAB

    Solving Schrödinger's Equation in 1,2,3-D with MATLAB

    February 19, 2019
    CSIRO: End-to-End Machine Learning Pipeline

    CSIRO: End-to-End Machine Learning Pipeline

    December 17, 2018
    Smart Lock: Assembly Programming, Product Realization, Marketing

    Smart Lock: Assembly Programming, Product Realization, Marketing

    July 18, 2018
    Custom Processor (Verilog), ISA, Compiler & Simulator (Python)

    Custom Processor (Verilog), ISA, Compiler & Simulator (Python)

    June 17, 2018
    DonateLK: Web Based Donation Platform

    DonateLK: Web Based Donation Platform

    November 18, 2017
    Gollum - Ring Finding Robot: [GPS, obstacle avoiding, wall following, color detection, parallel alignment]

    Gollum - Ring Finding Robot: [GPS, obstacle avoiding, wall following, color detection, parallel alignment]

    August 27, 2017
    Dobbybot: A Battlebot under $32

    Dobbybot: A Battlebot under $32

    July 18, 2016
    AutoCAD 3D: 3 Story House

    AutoCAD 3D: 3 Story House

    December 18, 2014
    Alexandria: Integrated Library System

    Alexandria: Integrated Library System

    November 18, 2012
    • Website
    • GitHub
    • Feed
    © 2026 Abarajithan G. Powered by Jekyll & Minimal Mistakes.